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ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 1 of 36 ibis4-14000 14 m pixel rolling shutter cmos image sensor datasheet
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 2 of 36 document history record issue date description of changes 1.0 11-aug-2003 document created. 1.1 16-sept-2003 p8: table 1: power dissipation updated. p8: table 2: qe*ff and sr*ff updated. 1.2 04-jan-2005 added cypress equivalent part number, part ordering table. added cypress document # 38-05709 rev ** in the document footer.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 3 of 36 1. preamble 1.1 overview this document describes the interfacing and the driving of the image sensor ibis4- 14000. the ibis4-14000 is a monochrome cmos active pixel image sensor. it is based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others). this datasheet allows the user to develop a camera system based on the described timing and interfacing. 1.2 main features the main features of the image sensor are identified as: ? 8x8 m 2 square pixels. ? 3048 x 4560 active pixels (13.9-mega-pixel). ? 36 x 24 mm 2 focal plane array (35 mm photographic film format). ? frame rate: 3 full frames/s (4 outputs). ? max. 15 mhz pixel clock rate. ? random programmable windowing and sub-sampling modes. ? electronic rolling shutter. ? 4 parallel analog outputs. ? optical dynamic range of 65 db. ? on-chip fixed pattern noise correction. 1.3 part number name package monochrome ibis4-14000-m CYII4SM014KAA-GBC ? (preliminary) ibis4-14000-c cyii4sc014kaa-gac ? (preliminary) 49-pins pga package monochrome
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 4 of 36 table of content 1. preamble............................................................................................................... 3 1.1 o verview .......................................................................................................3 1.2 m ain features ...............................................................................................3 1.3 p art number ..................................................................................................3 2. architecture..................................................................................................... 5 2.1 a rchitecture of the ibis4-14000 ? block diagram ................................5 2.2 p ixel specifications .....................................................................................7 3. specifications ................................................................................................... 8 3.1 g eneral specifications ................................................................................8 3.2 e lectro - optical specifications .................................................................8 3.3 s pectral response curve ............................................................................9 3.4 e lectrical specifications .........................................................................10 3.4.1 output stage ...........................................................................................10 3.4.2 absolute maximum ratings.....................................................................11 3.4.3 recommended operating specifications.................................................11 3.4.4 bias currents and references .................................................................12 3.4.5 handling ................................................................................................12 4. operation ........................................................................................................... 14 4.1 r eadout and sub - sampling modes ...........................................................14 4.2 s ensor output stage ..................................................................................16 4.2.1 amplifier specifications .........................................................................16 4.2.2 output amplifier crossbar switch (multiplexer).....................................16 4.3 s ensor readout timing diagrams ............................................................17 4.3.1 row sequencer .......................................................................................17 4.3.2 timing pulse pattern for readout of a pixel ...........................................21 4.3.3 fast frame reset timing diagram............................................................22 4.4 spi register .................................................................................................24 4.4.1 spi interface architecture......................................................................24 4.4.2 spi register definition ............................................................................24 5. pin configuration ........................................................................................ 27 6. geometry & mechanical.......................................................................... 30 6.1 d ie geometry ...............................................................................................30 6.2 p in number assignment ..............................................................................31 6.3 p ackage drawings ......................................................................................32 6.4 d ie placement dimensions and accuracy ...............................................33 6.5 c over glass .................................................................................................34 7. ordering information .............................................................................. 35
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 5 of 36 2. architecture 2.1 architecture of the ibis4-14000 ? block diagram the basic architecture of the sensor is shown in figure 1. pixel array 4560 x 3048 active pixels x-shift register y shift register 3048 column amplifiers 4560 row drivers y shift register 4560 row drivers clk_yr sync_yr analog outputs pixel (0,0) shs shr clk_ x sync_ x clk_yl sync_yl reset syr syl figure 1: imager architecture the y shift registers point at a row of the imager array. this row is selected and/or reset by the row drivers. there are 2 y shift registers: one points at the row that is read out and the second one points at the row to be reset. the second pointer may lead the first pointer by a specific number of rows. in that case, the time difference between both pointers is the integration time. alternatively, both shift registers be point at the same row for reset and readout for a faster reset sequence. when the row is read out, it is also reset in order to do double sampling for fixed pattern noise reduction. the pixel array of the ibis4-14000 consists of 4536 x 3024 active pixels and 24 additional columns and rows, which can also be addressed (see figure 2). the column amplifiers read out the pixel information and perform the double sampling operation. they also multiplex the signals on the readout busses, which are buffered by the output amplifiers.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 6 of 36 the shift registers can be configured for various sub-sampling modes. the output amplifiers can be individually powered down. and some other extra functions are foreseen. these options are configurable via a serial input port. 3024 x 4536 active p ixels 24 x 4536 dark p ixel s ------------- sky -------------- 3024 x 24 dark p ixel s 4 analog outputs to p of camera 3048 x 4560 total p ixels p ixel 0,0
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 7 of 36 2.2 pixel specifications select vddarray m1 m2 m3 reset output (column) figure 3: pixel schematic the pixel is a classic 3-transistor active pixel. the photodiode is a high-fill factor n- well/p-substrate diode. separate power supplies are foreseen: general power supply for the analog image core (vdd), power supply for the reset line drivers (vddr) and a separate power supply for the pixel itself (vddarray).
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 8 of 36 3. specifications 3.1 general specifications table 1: ibis4-14000 general specifications parameter value remark pixel architecture 3t pixel technology cmos pixel size 8 x 8 m 2 resolution 3048 x 4560 13.9 mega pixels power supply 3.3v shutter type electronic rolling shutter pixel rate 15 mhz nominal 20 mhz with extra power dissipation. power dissipation 176 mw 53 ma 3.2 electro-optical specifications table 2 lists the electro-optical specifications . all parameters are set using the default settings (see recommended operating conditions), unless otherwise specified. table 2: ibis4-14000 electro-optical specifications. parameter value remark effective conversion gain 18.5 v/e- see note 1. spectral response * fill factor 0.22 a/w (peak) peak q.e. * fill factor 40% between 500 and 700 nm. full well charge 64865 electrons see note 1. linear range 90 % of full well charge linearity definition: < 3% deviation from straight line through zero point. temporal noise (ktc noise limited) 35 electrons ktc noise, being the dominant noise source in the dark at short integration times. dynamic range 1871:1 (65.4 db) see note 1. linear dynamic range 1688:1 (64.5 db) see note 1. 3% deviation. average dark current 55 pa/cm 2 average value at 24 c lab temperature. dark current signal 223 electrons/s average value at 24 c lab temperature.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 9 of 36 parameter value remark 4.13 mv/s (average) limit tbd (10 mv/s) mtf at nyquist 0.55 in x 0.57 in y measured at 600 nm. fixed pattern noise (local) 0.11 % vsat rms average value of rms variation on local 32 x 32 pixel windows. fixed pattern noise (global) 0.15% vsat rms prnu <1% rms of signal anti-blooming 10 5 charge spill-over to neighboring pixels (= ccd blooming mechanism) notes: 1. settings: vdd=3.3 v, vddr =4v and vdd_array = 3v. 3.3 spectral response curve 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 400 500 600 700 800 900 1000 wavelength [nm] spectral response [a/w] x14 10% 20% 30% 40% figure 3: spectral response curve
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 10 of 36 3.4 electrical specifications 3.4.1 output stage unity gain buffers are implemented as output amplifiers. these amplifiers can directly be dc coupled to the analog-digital converter or coupled to an external programmable gain amplifier. the (dark reference) offset of the output signal is adjustable between 1.7 and 3 v. the amplifier output signal is negative going with increasing light levels, with a max. amplitude of 1.2 v (at 4v reset voltage, in hard reset mode). table 3 summarizes the electrical specifications. table 3: electrical specifications parameter value remark nominal power supply 3.3 v frame rate 3.25 frames/s (1) (1): 4 parallel analog outputs. (excluded readout of ?reset black? pixels). output signal amplitude 1.2 v negative signal polarity (lower signal for increasing light levels). output signal range 0.5 ? 3 v offset adjustable with darkref input pin slew rate to be measured can be tuned by resistor connected to obias pin settling time (stable output within 500 v from final value) to be measured notes on analog video signal and output amplifier specifications: 1. video polarity: the video signal is negative going with increasing light level. 2. signal offset: the analog offset of the video signal is settable by an external dc bias (pin 12 darkref). the settable range is between 1.7 and 3 v, with 2.65 v being the nominal expected set point. the output range (including 1.2 v video signal) is thus between 3 v and 0.5v. 3. power control: the output amplifiers can be switched between an ?operating? mode and a ?standby? mode via the serial port of the imager (see spi register configuration). 4. coupling: the ibis4-14000 can be dc or ac coupled to the ad converter.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 11 of 36 3.4.2 absolute maximum ratings table 4: absolute maximum ratings symbol parameter value unit v dc dc supply voltage -0.5 to +4.5 v v in dc input voltage -0.5 to v dc + 0.5 v v out dc output voltage -0.5 to v dc + 0.5 v i dc current per pin; any single input or output. 50 ma t stg storage temperature range. -10 to 66 (@ 15% rh) -10 to +38 (@ 86% rh) (rh = relative humidity) c altitude 8000 feet note : absolute ratings are those values beyond which damage to the device may occur. 3.4.3 recommended operating specifications table 5: recommended operating conditions symbol parameter min typ max unit vdd nominal power supply. 3.3 v vddrl vddrr reset power supply level. 4 v vdd_array pixel supply level. 3 v darkref dark reference offset level. 1.7 2.65 3 v gndab anti-blooming ground level. 0 0 1 v v out analog output level. 0.5 3 v v ih logic input high level. 2.5 3.3 v v il logic input low level. 0 1 v t a commercial operating temperature. 0 50 c (@ 15% rh) t a commercial operating temperature. 0 38 c (@ 86% rh)
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 12 of 36 3.4.4 bias currents and references table 6: bias input currents pin number pin name connection input current pin voltage 1 obias 10 k ? to vdd 179 ua 1.51 v 36 cbias 22 k ? to vdd 91 ua 1.29 v 37 pcbias 22 k ? to vdd 91 ua 1.29 v 48 xbias 10 k ? to vdd 181ua 1.49 v 49 abias gnd or open (or 10m to vdd) 0.8 v in case of 10 m tolerance on bias reference voltages: +/- 150 mv 3.4.5 handling 3.4.5.1 esd though not as sensitive as ccd sensors, the ibis4-14000 is vulnerable to esd like other standard cmos devices. take into account standard esd procedures when manipulating the device. 1) always discharge static electricity by grounding the human body and the instrument to be used. to ground the human body, provide a resistance of 1 mohm between the human body and the ground to be on the safe side. 2) when directly handling the device with the fingers, hold the part without the leads and do not touch any lead. 3) to avoid generating static electricity: i. do not scrub the glass surface with cloth or plastic ii. do not attach any tape or labels iii. do not clean the glass surface with dust-cleaning tape 4) when storing or transporting the device, put it in a container of conductive material.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 13 of 36 3.4.5.2 dust and contamination dust or contamination of the glass surface could deteriorate the output characteristics or cause a scar. in order to minimize dust or contamination on the glass surface, take the following precautions: 1) handle the device in a clean environment such as a cleaned booth (the cleanliness should be, if possible, class 100) 2) do not touch the glass surface with the fingers. 3) use gloves to manipulate the device 3.4.5.3 soldering soldering should be manually performed with 5 seconds at 350 c maximum at the tip of the soldering iron avoid mechanical stress when mounting the device.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 14 of 36 4. operation 4.1 readout and sub-sampling modes the sub-sampling modes available on the ibis4-14000 are summarized in table 7. table 7: sub-sample modes subsampling modes programmed into spi register x shift register subsampling settings bitcode mode use 000 001 010 1:1 full resolution (all columns) full resolution (4 outputs) 4:1 subsampling 011 24:1 select 4 columns/ skip 20 24:1 subsampling ( 2 outputs) 100 8:1 select 4 columns / skip 4s 8:1 subsampling (2 outputs) 101 12:1 select 4 columns / skip 8 12:1 subsampling (2 outputs) y shift register subsampling settings bitcode mode use 000 010 100 4:1 select 2 rows / skip 2 4:1 subsampling 001 1:1 full resolution (all rows) full resolution 011 6:1 select 2 rows / skip 4 6:1 subsampling 101 12:1 select 2 rows / skip 10 12:1 subsampling each mode is selected independently for the x and y shift registers. the sub- sampling mode is configured via the serial input port of the chip. the y and x shift
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 15 of 36 registers have some different sub-sampling m odes, due to constraints in the design of the chip. the baseline full resolution operation mode uses 4 outputs to read out the entire image. 4 consecutive pixels of a row are put in parallel on the 4 parallel outputs. sub-sampling is implemented by a shift regi ster with hard-coded sub-sample modes. depending on the selected mode, the shift register skips the required number of pixels when shifting the row or column pointer. the x shift register always selects 4 consecu tive columns in parallel. sub sampling in x can be done by activating one of the modes wherein a multiple of 4 consecutive columns is skipped on a clk_x pulse. the y shift register selects a single row. it will consecutively select 2 adjacent rows and then skip an amount of rows set by the sub sample mode. this implementation is chosen for easy sub sampling of color images through a 2-channel readout. in this way color data from 2x2 pixels is made available in all sub sample modes. on monochrome sensors this is not required, only one output can be used and the each second row selected by the y shift register can be skipped. this doubles the frame rate. note that for 2 or 1 channel readout, the not- used output amplifiers can be powered down through the spi shift register. rows can also be skipped by extra clk_y pulses. it is not required to apply additional control pulses to rows that are skipped. this is a way to implement extra sub-sampling schemes. for example, to support the 24:1 x shift register mode also vertically, the y shift register can be set to the 12:1 mode and an additional clk_y pulse needs to be given at the start of each row. table 8 lists the frame rates of the ibis4-14000 in various sub-sample modes with only one output. the row blanking time (dead time between readout of successive rows) has been set to 17.5 s. table 8: frame rates and resolution of theibis4-14000 in various sub-sampling modes ratio #outputs image resolution frame rate f rames/s frame readout time [s] 1:1 4 3024 x 4536 3.25 0.308 4:1 1 756 x 1134 12.99 0.077 8:1 1 378 x 567 41.30 0.024 12:1 1 252 x 378 77.13 0.013 note that the 24 additional columns and rows (see figure 2) do not sub sample.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 16 of 36 4.2 sensor output stage 4.2.1 amplifier specifications unity gain buffers are implemented as output amplifiers. paragraph 3.4 lists the specifications of the output amplifier stage. 4.2.2 output amplifier crossbar switch (multiplexer) a crossbar switch is available that routes the green pixels always to the same output (for a color device). the switch can be controlled automatically (with a toggle on every clk_y rising edge) or manually (through the spi register). figure 6 shows how it works. a pulse on sync_y resets the crossbar switch. the initial state after reset of the switchboard is read from the spi control register. when the automatic toggling of the switchboard is enabled, it toggles on every rising edge of the clk_y clock. separate pins are used for the sync_y and clk_y signals on the crossbar logic these pins can be connected to the sync_yl and clk_yl pins of the shift register that is used for readout. power power power power q sync_yr clk_yr manual figure 4: output amplifier crossbar switch
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 17 of 36 4.3 sensor readou t timing diagrams 4.3.1 row sequencer the row sequencer controls pulses to be given at the start of each new line. figure 7 shows the timing diagram for this sequence. the signals to be controlled at each row are: ? clk_yl and clk_yr: these are the clocks of the yl and yr shift register. they can be driven by the same signals and at a continuous frequency. at every rising edge, a new row is being selected. ? select: this signal selects the line that is currently sampled. it is important that pc and select are never active together. ? pc: an initialization pulse that needs to be given after the selection of a new row. ? shs (sample & hold pixel signal): this signal controls the track & hold circuits in the column amplifiers. it is used to sample the pixel signal in the columns. (0=track ; 1=hold) ? reset: this pulse resets the pixels of the row that is currently being selected. in rolling shutter mode, the reset signal is pulsed a second time to reset the row selected by the yr shift register. fo r ?reset black? dark reference signals, the reset pulse can be pulsed also during the first pc pulse. normally, reset and pc have a rising edge at the same position. the falling edge of reset lags behind the falling pc edge. ? shr (sample & hold pixel reset level): this signal controls another track & hold circuit in the column amplifiers. it is used to sample the pixel reset level in the columns (for double sampling). (0=track ; 1=hold) ? syl (select yl register): selects the yl shift register to drive the reset line of the pixel array ? syr (select yr register): selects the yr shift register to drive the reset line of the pixel array. for rolling shutter applications, syl and syr are complimentary. in full frame readout, both registers may be selected together, only if it is guaranteed that both shift registers point to the same row. this can reduce the row blanking time. ? sync_yr and sync_yl: synchronization pulse for the yr and yl shift registers. the sync_yr/sync_yl signal is clocked in during a rising edge
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 18 of 36 on clk_yr/clk_yl and resets the yr/yl shift register to the first row. both pulses are pulsed only once each frame. the exact pulsing scheme depends on the mode of use (full frame/ rolling shutter). a 200 ns set-up time applies. see further. clk_yr clk_yl sync_y r sync_y l shs reset shr syl sync_x a d e m g k clk_x (details on ro w readout diagram) once each f r ame for each new row syr c pc b d c a d optional reset pulse for reset black e o p q o p q select b b r r g figure 5: row sequencer timing diagram
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 19 of 36 ? sync_x: resets the column pointer to the first row. this has to be done before the end of the first pc pulse, in case when the previous line has not been read out completely. figure 5 shows the basic timing diagram of the ibis4-14000 image sensor and table 10 shows the timing specifications of the clocking scheme. table 9: timing specifications symbol min typ description a 6.8 us delay between falling edge on pc and rising edge on shs/shr. duration of shs/shr pulse. b 200 ns 600 ns min. sync setup times. sync_y is clocked in on rising edge on clk_y. sync_y pulse must overlap clk_y by one clock period. setup times of 200 ns apply after sync edges. within this setup time no rising clk edge may occur. c 2.7 us duration of pc pulse. d 4 us duration of reset pulse. e d + 2 * clk 0.5 us syl and syr pulses must overlap second reset pulse at both sides by one clock cycle. f 0us delay between rising edge on clk_yr and falling edge on select. g 1 clk 0.1 us delay between rising edge on shs and falling edge on select. k 1 clk 0.1 us delay between rising edge on shr and rising edge on syr m 17.5 us minimal total idle time between readout of two rows (vertical interval time). o 1.4 us delay between falling edge select and pc. p 5.4 us total select pulse duration (low period). q 1.3 us delay between rising edge on pc and rising edge on select. r 6.6 us delay between rising edge on select and rising edge on shs/shr. notes: clk = one clock period of the master clock, shortest system time period available.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 20 of 36 red items apply each row; green items apply once each frame. blue is for the additional reset for reset black pixels. in the above timing diagram, the yr shift register is used for the electronic shutter. the clk_yr is driven identically as clk_yl. the sync_yr pulse leads the sync_yl pulse by a given number of rows. relative to the row timing, both sync pulses are given at the same time position. sync_yr and sync_yl are only pulsed once each frame, sync_yl is pulsed when the first row will be read out and sync_yr is pulsed for the electronic shutter at the appropriate moment in time. this timing assumes that the registers that control the sub-sampling modes have been loaded in advance (through the spi interface), before the pulse on sync_yl or sync_yr. the second reset pulse and the pulses on syl and syr (all pulses drawn in red) are only applied when the rolling electronic shutter is used. for full frame integration, these pulses are skipped. the sync_y pulse is also used to initialise the switchboard (output multiplexer). this is also done by a synchronous reset on the rising edge of clk_y. normally the switchboard is controlled by the shift register used for readout (this is the yl shift register). this means that pin sync_y can be connected to sync_yl, and pin clk_y can be connected to clk_yl. the additional reset black pulse (indicated in blue in figure 5) can be given to make one or more lines black. this can be useful to generate a dark reference signal.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 21 of 36 4.3.2 timing pulse pattern for readout of a pixel figure 6 shows the timing diagram to preset (sync) the x shift register, read out the image row, and analog-digital conversion. there are 3 tasks: sync_x clk_x clk_adc (example) analog output pixel 1 pixel 2 pixel 3 x ts ts figure 6: pixel row read-out timing preset the x shift register : apply a low level to sync_x during a rising edge on clk_x at the start of a new row readout of the image row : pulse clk_x analog-digital conversion : clock the adc the sync pulses perform a synchronous reset of the shift registers to the first row/column on a rising edge on clk. this is identical for all shift registers (yr, yl and x). important : the sync_x signal has a set-up time ts of 150 ns. for the yr and ys shift registers, the set-up time is 200 ns. clk_x must be stable at least during this set-up time.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 22 of 36 in case where a partial row readout has been performed, 2 clk_x pulses (with sync_x = low) are required to fully deselect the column where the x pointer has been stopped. a single clk_x will leave the column partially selected, which will then have a different response when read out in the next row. when full row readout has been performed, the last column will be fully deselected by a single clk_x pulse (with sync_x=low). the x-register is reset by a single clk_x pulse (with sync_x=low). in case of partial row readout, the sync_x pulse has to be given before the sample pulses (shr and shs) of the row sampling process, in order to avoid a different response of the last column of the previous window. for the x shift register, the analog signal is delayed by 2 clock periods before it becomes available at the output (due to internal processing of the signal in the columns and output amplifier). the figure gives an example of an adc clock for an adc that samples on the rising edge. 4.3.3 fast frame reset timing diagram figure 9 shows the reset timing for a fast frame reset. syl and syr can be kept both high to make the reset mechanism faster and reduce propagation delays. pc, shs, shr can be kept high since they don?t interact with the pixel reset mechanism. table 10 lists timing specifications for reset, clk_y and select. table 10: timing specifications for fast reset (preliminary) symbol typical description a 0 us delay between rising clk_y edge and reset. b 4 us reset pulse width. c 0 reset hold time. d 1.6 us select pulse width. e 1 us setup hold time. constraint : a + e > 1 us due to propagation delay on pixel select line.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 23 of 36 clk_y r clk_yl sync_y r sync_yl shs rese t sh r syl syr pc b b a c select d e figure 7: fast frame reset timing
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 24 of 36 4.4 spi register 4.4.1 spi interface architecture the elementary unit cell of the serial to pa rallel interface consists of two d-flip-flops. the architecture is shown in figure 10. 16 of these cells connected in parallel, having a common /cs and sclk form the entire uploadable parameter block, where d in is connected to d out of the next cell. the uploaded settings are applied to the sensor on the rising edge of signal /cs. d q c d q c din to sensor core dout sclk cs 16 outputs to sensor core sclk din dout unity cell entire uploadable parameter block cs d0 d1 d2 d15 cs sclk din ts data valid tsclk th figure 8: uploadable parameter part table 11: timing requirements serial-parallel interface parameter value tsclk 100ns ts 50ns th 50ns 4.4.2 spi register definition sensor parameters can be serially uploaded inside the sensor at the start of a frame. the parameters are :
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 25 of 36 ? sub-sampling modes for x and y shift registers (3-bit code for 6 sub-sampling modes) ? sensor test mode and electrical black pixel mode ? power control of the output amplifiers, column amps and pixel array. each amplifier can be individually powered up/down ? output crossbar switch control bits. the crossbar switch is used to route the green pixels to the same output amplifiers at all time. a first bit controls the crossbar. when a second bit is set, the first bit will toggle on every clk_y edge in order to automatically route the green pixels of the bayer filter pattern. the code is uploaded serially as a 16-bit word (lsb uploaded first). table 12 lists the register definition. the default code for a full resolution readout is 33342 (decimal) or 1000 0010 0011 1110 table 12: serial sensor parameters register bit definitions bit description 0 (lsb) set to zero (0) 1 1= power on sensor array ; 0= power down 2 1 = power up output amplifier 4; 0 = power down 3 1 = power up output amplifier 3; 0 = power down 4 1 = power up output amplifier 2; 0 = power down 5 1 = power up output amplifier 1; 0 = power down 6 7 8 3 ?bit code for sub-sampling mode of x shift register: 000 = full resolution 011 = select 4, skip 20 001 = full resolution 100 = select 4, skip 4 010 = full resolution 101 = select 4, skip 8 9 10 11 3 ?bit code for sub-sampling mode of y shift registers: 000 = select 2, skip 2 011 = select 2, skip 4 001 = full resolution 100 = select 2, skip 2 010 = select 2, skip 2 101 = select 2, skip 2
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 26 of 36 bit description 12 crossbar switch (output multiplexer) control bit initial value. this initial value is clocked into the crossbar switch at a sync_yr rising edge pulse (when the array pointers jump back to row 1). the crossbar switch control bit selects the correspondence between multiplexer busses and output amplifiers. bus-to-output correspondence is according to the following table: bus when bit set to 0 when bit set to 1 1 output 1 output 2 2 output 2 output 1 3 (4 outputs) output 3 output 4 4 (4 outputs) output 4 output 3 13 1 = toggle crossbar switch control bit on every odd/even line. in order to let green pixels always use the same output amplifier automatically, this bit must be set to 1. on every clk_y rising edge (when a new row is selected), the crossbar switch control bit will toggle. initial value (after sync_y) is set by bit 12. 14 not used. 15 (msb) 1=power up sensor array ; 0 = power down 3 pins are used for the serial data interface. this interface converts the serial data into an (internal) parallel data bus (serial-parall el interface or spi). the control lines are: ? data : the data input. lsb is clocked in first. ? clk : clock, on each rising edge, the value of data is clocked in ? cs : chip select, a rising edge on cs loads the parallelized data into the on- chip register. the initial state of the register is undefined. however, no state exists that destroys the device.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 27 of 36 5. pin configuration table 13 lists the pin configuration of the ibis4-14000. figure 9 shows the assignment of pin numbers on the package. table 13: pin list pin nr. name function comment 1 obias bias current output amplifiers. connect with 20k ? to vdd and decouple with 100 nf to gnd. 2 gnd ground for output 3. 3 out3 output 3. 4 gnd ground for output 4. 5 out4 output 4. 6 vdd power supply. nominal 3.3 v 7 gnd ground. 0 v 8 out2 output 2. 9 gnd ground for output 2. 10 out1 output 1. 11 gnd ground for output 1. 12 darkref offset level of output signal. typ. 2.6 v. min. 1.7 v max. 3 v 13 temp1 temperature sensor. located near the output amplifiers (pixel 4536, 0) near the stitch line). any voltage above gnd forward biases the diode. connect to gnd if not used. 14 phdiode photodiode output. yields the equivalent photocurrent of 250 x 50 pixels. diode is located right under the pad. reverse biased by any voltage above gnd connect to gnd if not used. 15 clk_y y clock for switchboard. clocks on rising edge connect to clk_yl (or drive identically) 16 sync_y y sync pulse for switchboard. low active: synchronous sync on rising edge of clk_y connect to sync_yl (or drive identically) 17 temp2 temperature sensor. located near pixel (24,0). any voltage above gnd forward biases the diode. connect to gnd if not used.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 28 of 36 pin nr. name function comment 18 gndab anti-blooming reference level (=pin 33). typ. 0 v. set to 1.5 v for improved anti-blooming. 19 gnd ground. 0 v 20 vdd power supply. nominal 3.3 v 21 vddr power supply for reset line drivers = nominal 4 v connected on-chip to pin 30 22 clk_yr clock of yr shift register. shifts on rising edge. 23 syr activate yr shift register for driving of reset and select line of pixel array. high active. exact pulsing pattern see timing diagram. both syr = 1 and syl = 1 is not allowed, except when the same row is selected! 24 sync_yr sets the yr shift register to row 1. low active. synchronous sync on rising edge of clk_yr 200 ns setup time 25 vddarray pixel array power supply (= pin 26). 3 v 26 vddarray pixel array power supply (= pin 25). 3 v 27 sync_yl sets the yl shift register to row 1. low active. synchronous sync on rising edge of clk_yl 200 ns setup time. 28 syl activate yl shift register for driving of reset and select line of pixel array. high active. exact pulsing pattern see timing diagram. both syr = 1 and syl = 1 is not allowed, except when the same row is selected! 29 clk_yl clock of yl shift register. shifts on rising edge. 30 vddr power supply for reset line drivers. nominal 4 v. connected on-chip to pin 21. 31 vdd power supply. nominal 3.3 v 32 gnd ground. 0 v 33 gndab anti-blooming reference level (=pin 33). typ. 0 v. set to 1v for improved anti-blooming. 34 select control select line of pixel array. high active. see timing diagrams. 35 reset reset of the selected row of pixels. high active. see timing diagrams. 36 cbias bias current column connect with 22 k ? to vdd
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 29 of 36 pin nr. name function comment amplifiers. and decouple with 100 nf to gnd. 37 pcbias bias current. connect with 22 k ? to vdd and decouple with 100 nf to gnd. 38 din serial data input. 16-bit word. lsb first. 39 sclk spi interface clock. shifts on rising edge. 40 cs chip select. data copied to registers on rising edge. 41 pc row initialization pulse. see timing diagrams. 42 sync_x sets the x shift register to row 1. low active. synchronous sync on rising edge of clk_x 150 ns setup time. 43 gnd ground. 0 v 44 vdd power supply. nominal 3.3 v 45 clk_x clock of yr shift register. shifts on rising edge. 46 shr row track & hold reset level (1=hold; 0=track). see timing diagram. 47 shs row track & hold signal level (1=hold; 0=track). see timing diagram. 48 xbias bias current x multiplexer. connect with 10 k ? to vdd and decouple with 100 nf to gnd. 49 abias bias current pixel array. connect with 10 m ? to vdd and decouple with 100 nf to gnd. not used . may also be disconnected or grounded
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 30 of 36 6. geometry & mechanical 6.1 die geometry ground pad, also connected to package ground plane analog output pad ground for output pad (not connected to package ground plane) locations of temperature sensing diodes location of photodiode array 4 output channels p ixel 0,0 500 m pin 1 figure 9: die geometry and location of pixel (0,0)
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 31 of 36 6.2 pin number assignment package back side 1 2 3 4 5 6 13 12 11 10 9 8 7 19 18 17 16 15 14 20 21 22 23 24 25 31 30 29 28 27 26 32 33 34 35 36 37 38 39 40 41 42 43 49 48 47 46 45 44 figure 10: pin number assignment. ?solid? drawn pins are connected to die attach area for a proper ground plane.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 32 of 36 6.3 package drawings
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 33 of 36 6.4 die placement dimensions and accuracy 200 2
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 34 of 36 6.5 cover glass schott d-263 plain glass will be as cover glass of the ibis4-14000. 0 10 20 30 40 50 60 70 80 90 100 400 500 600 700 800 900 wavelength [nm] transmission [%] figure 10: d-263 transmittance curve
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 35 of 36 7. ordering information table 14: fillfactory and cypress part numbers fillfactory part number cypress semiconductor part number ibis4-14000-c cyii4sc014kaa-gac ? (preliminary) ibis4-14000-m CYII4SM014KAA-GBC ? (preliminary) disclaimer fillfactory image sensors are only warranted to meet the specifications as described in the production data sheet. fillfactory reserves the right to change any information contained herein without notice. please contact info@fillfactory.com for more information.
ibis4-14000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact info@fillfactory.com document #:38-05709 rev.**(revision 1.2) page 36 of 36 document history page document title: ibis4-14000 14m pixel rolling shutter cmos image sensor document number: 38-05709 rev. ecn no. issue date orig. of change description of change ** 310213 see ecn sil initial cypress release (eod)

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